Architecture design methods for application domain-specific uintegrated computer systems
|Organizations:||University of Oulu, Faculty of Technology, Department of Electrical and Information Engineering
|Online Access:||PDF Full Text (PDF, )|
|Persistent link:|| http://urn.fi/urn:isbn:9513863646
|Publish Date:|| 2005-03-01
|Thesis type:||Doctoral Dissertation
|Defence Note:||Academic dissertation to be presented with the assent of the Faculty of Technology, University of Oulu, for public discussion in Kajaaninsali (L6), Linnanmaa, Oulu, on May 7th, 2004, at 12 noon.
Professor Jari Nurmi
Professor Jorma Skyttä
Professor Hannu Heusala
The role of the single computer inside application-specific integrated circuits is changing with the increasing capacity of semiconductor technology. The system functionality can be partitioned to a set of communicating application domain-specific computers instead of developing the most efficient general-purpose computers that fulfil all kinds of computing needs. The main design challenges are the complexity and diversity of application-domains and the complexity of platforms which can provide enough capacity for those applications.
The architecture design methods presented in this thesis are targeted at application domain-specific computers that are implemented as integrated circuits. Backbone-platform-system design methodology separates the technology, platform design efficiency and application development problems from each other. It also provides a system design framework for the architecture design methods presented. The methods are based on complexity, mappability, and capacity-based quality estimations that are used as decision support and quality validation tools. Abstract models of both applications and architectures enable rapid estimations and adequate coverage in design space exploration.
The methods have been applied to various case examples. Complexity-based estimation provided a systematic approach to the selection of an architecture template that takes into account the changes in technologies and design efficiency. Mappability-based processor-algorithm quality estimation enabled us to study more than 10,000 processor architectures for WLAN modem transceiver example. Capacity-based quality estimation was used in the performance evaluation of configurable multiprocessor architecture. In all cases the respective simulations using for example instruction-set simulators would have taken much longer and required advanced post-processing of results.
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