Integrated RF building blocks for base station applications
1University of Oulu, Faculty of Technology, Department of Electrical and Information Engineering
|Online Access:||PDF Full Text (PDF, 1.8 MB)|
|Persistent link:|| http://urn.fi/urn:isbn:951426908X
|Publish Date:|| 2003-01-10
|Thesis type:||Doctoral Dissertation
|Defence Note:||Academic Dissertation to be presented with the assent of the Faculty of Technology, University of Oulu, for public discussion in Kajaaninsali (Auditorium L6), Linnanmaa, on January 10th, 2003, at 12 noon.
Professor Mohammed Ismail
Professor Torben Larsen
This thesis studies the level of performance achievable using today's standard IC processes in the integrated RF subcircuits of the modern GSM base station. The thesis concentrates on those circuit functions, i.e. I/Q modulators, variable gain amplifiers and frequency synthesizers, most relevant for integration in the base station environment as pinpointed by studying the receiver/transmitter architectures available today.
Several RF integrated circuits have been designed, fabricated and their level of performance measured. All main circuits were fabricated in a standard double-metal double-poly 1.2 and 0.8 μm BiCMOS process. Key circuit structures and their measured properties are: 90° phase shifter with ±1° phase error with VCC = 4.5…5.5 V and T = -10…+85 °C, I/Q modulator suitable for operation at output frequencies from 100 MHz to 1 GHz and baseband frequencies from 60 to 500 kHz (2.0 mm × 2.0 mm, 100 mA, 5.0 V) with LO suppression of 38 dBc and image rejection of 41 dBc, temperature compensated DC to 1.5 GHz variable gain amplifier (1.15 mm × 2.00 mm, 100 mA, 5.0 V) with a linear 50 dB gain adjustment range, maximum gain of 18.5 dB and gain variation of 1 dB up to 700 MHz over the whole operating conditions range of VCC = 4.5…5.5 V and T = -10…+85 °C, a complete bipolar semicustom synthesizer (90…122 mA, 5.0 V) and two complete full-custom BiCMOS synthesizer chips including all building blocks of a PLL-based synthesizer except for the voltage controlled oscillator and the loop filter. The synthesizers include circuit structures such as ∼2 GHz multi-modulus divider and low-noise programmable phase detector/charge pump (18.7 pA/√Hz at Iout = 500 μA) and have an exemplar phase noise performance of -110 dBc/Hz at 200 kHz offset.
One of the main problems of the integer-N PLL based synthesizer when used in a multichannel telecommunications system is the level of spurious signals at the output, when the synthesizer is optimised for fast frequency switching. Therefore, a method using only two current pulses to make the frequency step response of the loop faster, thus allowing a narrower loop bandwidth to be used for additional spur suppression, is proposed. The operation of the proposed speed-up method is analysed mathematically and verified by measurements of an existing RF-IC synthesizer operating at 800 MHz. Measurements show that simple current pulses can be used to speed up the channel switching of a practical RF synthesizer having a frequency step time in the tens of μs range. In the example, a 7.65 MHz frequency step was made seven times faster using the proposed method.
Acta Universitatis Ouluensis. C, Technica
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