Non-coherent energy detection transceivers for Ultra Wideband Impulse radio systems
|Organizations:||University of Oulu, Faculty of Technology, Department of Electrical and Information Engineering
University of Oulu, Centre for Wireless Communications
University of Oulu, Infotech Oulu
|Online Access:||PDF Full Text (PDF, 2.1 MB)|
|Persistent link:|| http://urn.fi/urn:isbn:9789514287176
|Publish Date:|| 2008-01-29
|Thesis type:||Doctoral Dissertation
|Defence Note:||Academic dissertation to be presented, with the assent of the Faculty of Technology of the University of Oulu, for public defence in Raahensali (Auditorium L10), Linnanmaa, on February 8th, 2008, at 12 noon
Doctor John R. Farserotu
Professor Kari Halonen
The focus of this thesis is Ultra Wideband (UWB) Impulse Radio (UWB-IR) transmitters and non-coherent receivers. The aim of the thesis is to investigate, analyze and design UWB-IR transmitter and receiver structures both from a theoretical and circuit design viewpoint.
An UWB-IR transmitter structure is proposed and is the subject of a detailed investigation. The transmitter generates a Gaussian monocycle and can be modified to generate a family of Gaussian waveforms. The Gaussian monocycle is easy to generate while providing good bit-error-rate (BER) performance. The Gaussian monocycle has a wide -10 dB bandwidth and a zero-DC component which does not decrease antenna efficiency. The transmitter design includes a delay locked loop (DLL) based frequency synthesis approach. The advantage of using a frequency synthesis approach based on a DLL is based on the fact that a DLL generates less noise than a phase locked loop (PLL) and is inherently stable. The generated pulse has a width of less than 350 ps and a -10 dB bandwidth of 4.7 GHz. The power consumption of the designed UWBIR transmitter is 20 mW at a voltage supply of 3.3 V. Compared with other integrated UWB-IR transmitters, the transmitter presented in this thesis has the lowest pulse width for comparable integrated processes, one of the lower power consumptions and a low die area.
The BER performance of several UWB-IR non-coherent receiver structures is presented. The energy detection (ED) receiver offers the same BER performance as the transmitted reference scheme with binary pulse amplitude modulation (BPAM) but has a lower implementation complexity since it does not require an analogue delay line in its structure.
Circuit performance of several blocks of the ED receiver is presented. The radio frequency (RF) front-end and analogue baseband sections of the receiver have been designed as an integrated circuit (IC) in a 0.35 μm bipolar complementary metal oxide semiconductor (BiCMOS) process. The RF front-end section includes a low noise amplifier (LNA), a variable gain amplifier (VGA) and a Gilbert cell. The LNA has a noise figure (NF) of less than 3 dB, a gain of 18 dB in the interest bandwidth and less than 20 mW of power consumption. The NF of the LNA can be reduced even further at the expense of a higher power consumption or by using input pads with lower capacitance values. The noise figure can be also lowered by using a process which provides transistors with higher transit frequency (fT). Trading-off power consumption for noise is still a key design issue in the design of integrated UWB-IR receivers.
The analogue baseband section includes a bank of integrators and a 4-bit analogue to digital converter (ADC). The ADC is running at a sampling rate equal to the symbol rate and takes only 2 mW of power at 3.3 V supply. The power consumption of the designed integrated front-end and analogue baseband receiver sections is 117 mW at a power supply of 3.3 V.
The digital baseband of the receiver have been implemented on a field programmable gate array (FPGA) technology. The power consumption of the baseband is 450 mW with a power supply of 1.2 V and a maximum supply of 3.3 V for input-output pins.
The total power consumption of the designed transceiver is 587 mW. When compared with other UWB receiver architectures, the energy detection receiver has the lowest power consumption due to the low power consumption of the LNA, simple synchronization architecture and low sampling rate of the ADC.
Acta Universitatis Ouluensis. C, Technica
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