University of Oulu

M. Safarpour, R. Inanlou, M. Charmi, O. Shoaei and O. Silvén, "ADC-Assisted Random Sampler Architecture for Efficient Sparse Signal Acquisition," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems. doi: 10.1109/TVLSI.2018.2821696

ADC-assisted random sampler architecture for efficient sparse signal acquisition

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Author: Safarpour, Mehdi1; Inanlou, Reza2; Charmi, Mostafa3;
Organizations: 1University of Oulu, FI-90014 Oulu, Finland
2University of Tehran, Tehran 1417466191, Iran
3University of Zanjan, Zanjan 4537138791, Iran
Format: article
Version: accepted version
Access: open
Online Access: PDF Full Text (PDF, 0.5 MB)
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Language: English
Published: Institute of Electrical and Electronics Engineers, 2018
Publish Date: 2018-04-18


A method for sampling Fourier sparse signals for efficient implementation of analog-to-information converters is proposed. The solution reconstructs Nyquist rate high-resolution signal from Nyquist rate low-resolution and sub-Nyquist rate high-resolution samples. For implementation, an architecture based on customized reconfigurable successive approximation register analog-to-digital converter is proposed, simulated, and demonstrated. The power consumption with a 90-nm CMOS process is less than 26 μW with 1-Msample/s rate in reconfigurable 3/10-bit mode. The number of floating point operations per second needed for signal recovery is less than 2% required by the orthogonal matching pursuit algorithm. The functionality of the solution has been verified with an experimental system.

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Series: IEEE transactions on very large scale integration (VLSI) systems
ISSN: 1063-8210
ISSN-E: 1557-9999
ISSN-L: 1063-8210
Volume: In presss
DOI: 10.1109/TVLSI.2018.2821696
Type of Publication: A1 Journal article – refereed
Field of Science: 113 Computer and information sciences
213 Electronic, automation and communications engineering, electronics
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