A fully integrated 4 × 2 element CMOS RF phased array receiver for 5G
|Author:||Shaheen, Rana A.1; Akbar, Rehman1; Sethi, Alok1;|
1Center for Wireless Communication – Radio Technologies, University of Oulu
2Electronics Laboratory – Circuits and Systems, University of Oulu
|Persistent link:|| http://urn.fi/urn:nbn:fi-fe2018121851148
|Publish Date:|| 2019-06-29
This paper presents a fully integrated phased array receiver containing two four element radio frequency (RF) beamforming receivers supporting two multiple-input multiple-output channels. The receivers are designed and fabricated using 45 nm CMOS SOI technology. A 10 bit IQ vector modulator phase shifter (IQVM) is implemented in RF signal paths to control the phase and amplitude of the received signal before combining. Each IQVM provides 360° phase shift control and 17 dB gain variation. An off-chip, simultaneous high-Q impedance matching and bandpass filtering technique for each low-noise amplifiers is presented using non-uniform transmission line segments. Measured downconversion gain at 100 MHz intermediate frequency and noise figure (NF) of a single path are 23 and 5.4 dB, respectively, giving estimated 3.4 dB NF for a single element when simulated PCB and matching losses are taken into account. 1 dB compression point and Input third-order intercept point (IIP3) are − 37 and − 28 dBm, respectively. Each four-element receiver consumes 486 mW DC power from 1.2 V power supply. Total area of two receivers is 5.69 mm².
Analog integrated circuits and signal processing
|Type of Publication:||
A1 Journal article – refereed
|Field of Science:||
213 Electronic, automation and communications engineering, electronics
This research has been financially supported by Nokia Corporation and Academy of Finland 6Genesis Flagship (Grant 318927).
|Academy of Finland Grant Number:||
318927 (Academy of Finland Funding decision)
© Springer Science+Business Media, LLC, part of Springer Nature 2018. This is a post-peer-review, pre-copyedit version of an article published in Analog Integrated Circuits and Signal Processing. The final authenticated version is available online at: https://doi.org/10.1007/s10470-018-1251-0.