CMOS technology scaling advantages in time domain signal processing |
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Author: | Jansson, Jussi-Pekka1; Keränen, Pekka1; Kostamovaara, Juha1; |
Organizations: |
1Circuits and Systems Research Group, University of Oulu, Oulu 90014, Finland 2Department of Physics, University of Milano- Bicocca, Milano 20126, Italy |
Format: | article |
Version: | accepted version |
Access: | open |
Online Access: | PDF Full Text (PDF, 0.3 MB) |
Persistent link: | http://urn.fi/urn:nbn:fi-fe2018121851276 |
Language: | English |
Published: |
Institute of Electrical and Electronics Engineers,
2017
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Publish Date: | 2018-12-18 |
Description: |
AbstractThis paper compares two CMOS technologies, the robust 350nm version and its modern 28nm successor, in terms of time-domain signal processing parameters. The evaluated parameters; propagation delay, delay variation due to process and mismatch fluctuations, sensitivity to noise and area and power usage are crucial especially in measurement devices relying on precise timings, high precision time-to-digital converters, for example. Post-layout simulations show that the modern scaled technology offers superior speed, efficient area usage and low power consumption but suffers from considerable delay mismatch. Therefore applications relying on precise time domain signal processing do not always benefit from technology scaling. see all
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ISBN: | 978-1-5090-3596-0 |
ISBN Print: | 978-1-5090-3597-7 |
Pages: | 1 - 5 |
DOI: | 10.1109/I2MTC.2017.7969659 |
OADOI: | https://oadoi.org/10.1109/I2MTC.2017.7969659 |
Host publication: |
2017 IEEE International Instrumentation and Measurement Technology Conference (I2MTC) |
Conference: |
IEEE International Instrumentation and Measurement Technology Conference |
Type of Publication: |
A4 Article in conference proceedings |
Field of Science: |
213 Electronic, automation and communications engineering, electronics |
Subjects: | |
Copyright information: |
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