An 80 × 25 pixel CMOS single-photon image sensor with sub-ns time gating for solid state 3D scanning |
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Author: | Ruokamo, Henna1; Rapakko, Harri1; Kostamovaara, Juha1 |
Organizations: |
1Faculty of Information Technology and Electrical Engineering, Circuits and Systems Research Unit, University of Oulu, Finland |
Format: | article |
Version: | accepted version |
Access: | open |
Online Access: | PDF Full Text (PDF, 0.3 MB) |
Persistent link: | http://urn.fi/urn:nbn:fi-fe2018122051448 |
Language: | English |
Published: |
Institute of Electrical and Electronics Engineers,
2017
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Publish Date: | 2018-12-20 |
Description: |
AbstractImager topology with sub-ns time gating for 3D distance measurement application and first measurement results of the prototype are presented. The imager has a fully digital operating principle with single-photon avalanche diode detectors and on-chip narrow gating of pixel groups. The prototype detector has 80 × 25 pixels with a fill factor of 34 % in the sensor area. The chip has been fabricated in a 0.35 μm high-voltage process and occupies 5.69 × 5.02 mm2 area. see all
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ISBN: | 978-1-5090-6508-0 |
ISBN Print: | 978-1-5090-6507-3 |
Pages: | 365 - 368 |
DOI: | 10.1109/PRIME.2017.7974183 |
OADOI: | https://oadoi.org/10.1109/PRIME.2017.7974183 |
Host publication: |
2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) |
Conference: |
Conference on Ph.D. Research in Microelectronics and Electronics |
Type of Publication: |
A4 Article in conference proceedings |
Field of Science: |
213 Electronic, automation and communications engineering, electronics |
Subjects: | |
Funding: |
The authors acknowledge financial support from the Academy of Finland (Centre of Excellence in Laser Scanning Research) and the Infotech Oulu Graduate School. |
Copyright information: |
© 2017 IEEE. Translations and content mining are permitted for academic research only. Personal use is also permitted, but republication/redistribution requires IEEE permission. |