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H. Ruokamo, L. Hallman, H. Rapakko and J. Kostamovaara, "An 80 × 25 pixel CMOS single-photon range image sensor with a flexible on-chip time gating topology for solid state 3D scanning," ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference, Leuven, 2017, pp. 59-62. doi: 10.1109/ESSCIRC.2017.8094525

An 80 × 25 pixel CMOS single-photon range image sensor with a flexible on-chip time gating topology for solid state 3D scanning

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Author: Ruokamo, Henna1; Hallman, Lauri1; Rapakko, Harri1;
Organizations: 1Faculty of Information Technology and Electrical Engineering, Circuits and Systems Research Unit, University of Oulu, Finland
Format: article
Version: accepted version
Access: open
Online Access: PDF Full Text (PDF, 0.3 MB)
Persistent link: http://urn.fi/urn:nbn:fi-fe2018122051449
Language: English
Published: Institute of Electrical and Electronics Engineers, 2017
Publish Date: 2018-12-20
Description:

Abstract

A solid state 3D scanner based on a pulsed laser diode source and narrow time gating of a 2D CMOS single photon avalanche diode (SPAD) detector array is presented. The imager uses an on-chip delay-locked loop to program the time gating of 40 sub-arrays individually. The prototype detector has 80 × 25 pixels with a fill factor of 32 % in the sensor area. The chip has been fabricated in a 0.35 μm high-voltage process and occupies a 5.69 × 5.02 mm 2 area. A 3D range image rate of ~5 frames/second with centimeter level precision is demonstrated to passive targets within a range of ~1 meter and FOV of 36 × 57 degrees.

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ISBN: 978-1-5090-5025-3
ISBN Print: 978-1-5090-5026-0
Pages: 59 - 62
DOI: 10.1109/ESSCIRC.2017.8094525
OADOI: https://oadoi.org/10.1109/ESSCIRC.2017.8094525
Host publication: ESSCIRC 2017 : 43rd IEEE European Solid State Circuits Conference
Conference: IEEE European Solid State Circuits Conference
Type of Publication: A4 Article in conference proceedings
Field of Science: 213 Electronic, automation and communications engineering, electronics
Subjects:
3D scanner
SPAD Array
single-photon avalanche diode (SPAD)
time gating
Article
Funding: The authors acknowledge financial support from the Academy of Finland (Centre of Excellence in Laser Scanning Research) and the Infotech Oulu Graduate School.
Copyright information: © 2017 IEEE. Translations and content mining are permitted for academic research only. Personal use is also permitted, but republication/redistribution requires IEEE permission.