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Optimum number of transistors in stacked CMOS millimeter-wave power amplifiers |
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| Author: | Montaseri, Mohammad Hassan1; Aikio, Janne1; Rahkonen, Timo1; |
| Organizations: |
1Centre for Wireless Communications and Circuits and Systems Research Group Faculty of Information Technology and Electrical Engineering (ITEE) University of Oulu Oulu, Finland |
| Format: | article |
| Version: | accepted version |
| Access: | open |
| Online Access: | PDF Full Text (PDF, 0.6 MB) |
| Persistent link: | http://urn.fi/urn:nbn:fi-fe201902134733 |
| Language: | English |
| Published: |
Institute of Electrical and Electronics Engineers,
2018
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| Publish Date: | 2019-02-13 |
| Description: |
AbstractThis paper proposes how to define the optimum number of stacked transistors in a multi-stacked CMOS power amplifier (PA) topology, based on several physical as well as circuit design aspects. Starting with a systematic concept, the analysis then goes through the relevance of transistor transconductance, aspect ratio, parasitics, operating frequency, and the number of transistor stages in a pentagonal trade-off concept. While this is done based on theoretical circuit analysis, the results, then, are evaluated using simulations based on 45nm CMOS technology. see all
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| Series: |
IEEE International Conference on Circuits and Systems |
| ISSN: | 2379-4461 |
| ISSN-E: | 2379-447X |
| ISSN-L: | 2379-4461 |
| ISBN: | 978-1-5386-4881-0 |
| ISBN Print: | 978-1-5386-4882-7 |
| Article number: | 8351160 |
| DOI: | 10.1109/ISCAS.2018.8351160 |
| OADOI: | https://oadoi.org/10.1109/ISCAS.2018.8351160 |
| Host publication: |
2018 IEEE International Symposium on Circuits and Systems (ISCAS). 27-30 May 2018, Florence, Italy |
| Conference: |
IEEE International Symposium on Circuits and Systems |
| Type of Publication: |
A4 Article in conference proceedings |
| Field of Science: |
213 Electronic, automation and communications engineering, electronics |
| Subjects: | |
| Copyright information: |
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