Boutellier, J. & Nyländen, T. J Sign Process Syst (2017) 89: 469. https://doi.org/10.1007/s11265-017-1260-8
Design flow for GPU and multicore execution of dynamic dataflow programs
|Author:||Boutellier, Jani1,2; Nylanden, Teemu1|
1Center for Machine Vision and Signal Analysis, University of Oulu, Oulu, Finland
2Present address: Laboratory of Pervasive Computing, Tampere University of Technology, Tampere, Finland
|Online Access:||PDF Full Text (PDF, 0.3 MB)|
|Persistent link:|| http://urn.fi/urn:nbn:fi-fe201902215892
|Publish Date:|| 2018-06-24
Dataflow programming has received increasing attention in the age of multicore and heterogeneous computing. Modular and concurrent dataflow program descriptions enable highly automated approaches for design space exploration, optimization and deployment of applications. A great advance in dataflow programming has been the recent introduction of the RVC-CAL language. Having been standardized by the ISO, the RVC-CAL dataflow language provides a solid basis for the development of tools, design methodologies and design flows. This paper proposes a novel design flow for mapping RVC-CAL dataflow programs to parallel and heterogeneous execution platforms. Through the proposed design flow the programmer can describe an application in the RVC-CAL language and map it to multi- and many-core platforms, as well as GPUs, for efficient execution. The functionality and efficiency of the proposed approach is demonstrated by a parallel implementation of a video processing application and a run-time reconfigurable filter for telecommunications. Experiments are performed on GPU and multicore platforms with up to 16 cores, and the results show that for high-performance applications the proposed design flow provides up to 4 × higher throughput than the state-of-the-art approach in multicore execution of RVC-CAL programs.
Journal of signal processing systems for signal image and video technology
|Pages:||469 - 478|
|Type of Publication:||
A1 Journal article – refereed
|Field of Science:||
213 Electronic, automation and communications engineering, electronics
The authors thank anonymous reviewers for their constructive comments. This work was funded by the Academy of Finland project UNICODE.
|Academy of Finland Grant Number:||
274911 (Academy of Finland Funding decision)
© Springer Science+Business Media, LLC 2017. This is a post-peer-review, pre-copyedit version of an article published in Journal of signal processing systems for signal, image, and video technology. The final authenticated version is available online at: https://doi.org/10.1007/s11265-017-1260-8.