M. Neitola, "Two-Stage Internal DAC Mismatch Mitigation for a Continuous-Time Delta-Sigma ADC," 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), Helsinki, Finland, 2019, pp. 1-7. doi: 10.1109/NORCHIP.2019.8906920
Two-stage internal DAC mismatch mitigation for a continuous-time delta-sigma ADC
1CAS research unit, Faculty of Information Technology and Electrical Engineering, University of Oulu, Finland
|Online Access:||PDF Full Text (PDF, 0.4 MB)|
|Persistent link:|| http://urn.fi/urn:nbn:fi-fe2019121748438
Institute of Electrical and Electronics Engineers,
|Publish Date:|| 2019-12-17
For continuous-time multi-bit Delta-Sigma data converters, mitigating the dynamic mismatch of the multi-bit digital-to-analog converter (DAC) with the so-called ISI-shaping DAC-encoder is a currently active research topic. ISI-shaper linearizes both static and dynamic DAC mismatch via spectral shaping of mismatch noise. However, such encoder may be too timing-, area-or power-critical for Delta-Sigma analog-to-digital converters. This paper proposes a novel approach viable for Delta-Sigma analog-to-digital data conversion. Here, the static portion of the DAC mismatch is linearized in the DAC feedback and the dynamic portion will be linearized digitally. Measuring and storing the ISI-error digitally requires error calibration for which this paper suggests an online approach. The proposed digital ISI-error correction can be used for both one-and multi-bit data converters.
|Pages:||1 - 7|
2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) 29-30 Oct 2019 Helsinki, Finland
IEEE Nordic Circuits and Systems Conference
|Type of Publication:||
A4 Article in conference proceedings
|Field of Science:||
213 Electronic, automation and communications engineering, electronics
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