J. Rusanen, M. Hietanen, A. Sethi, T. Rahkonen, A. Pärssinen and J. P. Aikio, "Ka-Band Stacked Power Amplifier on 22 nm CMOS FDSOI Technology Utilizing Back-Gate Bias for Linearity Improvement," 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), Helsinki, Finland, 2019, pp. 1-4. doi: 10.1109/NORCHIP.2019.8906915
Ka-band stacked power amplifier on 22 nm CMOS FDSOI technology utilizing back-gate bias for linearity improvement
|Author:||Rusanen, Jere1; Hietanen, Mikko1; Sethi, Alok1;|
1University of Oulu, Finland
|Online Access:||PDF Full Text (PDF, 0.5 MB)|
|Persistent link:|| http://urn.fi/urn:nbn:fi-fe2019121748458
Institute of Electrical and Electronics Engineers,
|Publish Date:|| 2019-12-17
This paper presents a method for extending millimeter wave power amplifier (PA) linear range by fine tuning the CMOS SOI device output characteristics via back-gate biasing. The effect of back-gate biasing to PA performance is measured and reported. It is demonstrated how implementing the same bias point with different back-gate values affects the linear range of the fabricated PA. By applying positive back-bias to the NFET devices, the measured PA displays minimum AM-PM and reaches maximum output power, PAE and 1 dB compression point of 16.3 dBm, 23 % and 13.9 dBm, respectively. EVM of 6.8 % and ACLR of −29.3 dBC were achieved at 5 dBm average output channel power with a 100MHz 64-QAM OFDM signal.
|Pages:||1 - 4|
2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)
IEEE Nordic Circuits and Systems Conference
|Type of Publication:||
A4 Article in conference proceedings
|Field of Science:||
213 Electronic, automation and communications engineering, electronics
This research has been financially supported by Academy of Finland 6Genesis Flagship (grant 318927) and Infotech Oulu.
|Academy of Finland Grant Number:||
318927 (Academy of Finland Funding decision)
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