R. A. Shaheen, T. Rahkonen, R. Akbar, J. P. Aikio, A. Sethi and A. Pärssinen, "Layout Optimization Techniques for $r_{g}$ and, $f_{max}$ of Cascode Devices for mm Wave Applications," 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), Helsinki, Finland, 2019, pp. 1-4. doi: 10.1109/NORCHIP.2019.8906913

### Layout optimization techniques for $$r_{g}$$ and, $$f_{max}$$ of Cascode devices for mm wave applications

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Author: Shaheen, Rana A.1; Rahkonen, Timo1; Akbar, Rehman1;
Organizations: 1University of Oulu, Finland
Format: article
Version: accepted version
Access: open
Online Access: PDF Full Text (PDF, 1 MB)
Persistent link: http://urn.fi/urn:nbn:fi-fe202001071215
Language: English
Published: Institute of Electrical and Electronics Engineers, 2019
Publish Date: 2020-01-07
Description:

# Abstract

A common-source cascode device is commonly used in amplifier designs at RF/mmWave frequencies. In addition to intrinsic parasitic components, extrinsic components due to wiring and layout effects, also play an important role towards performance and accurate modelling of the devices. In this work, a comparison of two different layout techniques for cascode devices is presented, to reduce the extrinsic parasitic elements, such as gate resistance. A multi-gate or multi-port layout technique is proposed for optimizing the gate resistance $$r_{g}$$. Two separate structures are designed and fabricated using 45nm CMOS SOI technology. Extracted values from measurement results show reduction of 10% in $$r_{g}$$ of multi-gate layout technique compared to a conventional gate-above-device layout for cascode devices. However, conventional layout exhibits smaller gate to source and gate-to-drain capacitances which leads to better performance in terms of speed, i.e. $$f_{max}$$.

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ISBN: 978-1-7281-2769-9
ISBN Print: 978-1-7281-2770-5
Pages: 1 - 4
DOI: 10.1109/NORCHIP.2019.8906913
OADOI: https://oadoi.org/10.1109/NORCHIP.2019.8906913
Host publication: 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)
Conference: IEEE Nordic Circuits and Systems Conference
Type of Publication: A4 Article in conference proceedings
Field of Science: 213 Electronic, automation and communications engineering, electronics
Subjects:
Funding: The authors would like to thank Nokia Corporation for financial support and Global Foundries for support in process technology. Lab assistance from Matti Polojarvi is highly acknow ledged. This research has been also in part financially supported by Academy of Finland 6Genesis Flagship (grant 318927).
Academy of Finland Grant Number: 318927
Detailed Information: 318927 (Academy of Finland Funding decision)
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