University of Oulu

M. A. Elmohr et al., "RVNoC: A Framework for Generating RISC-V NoC-Based MPSoC," 2018 26th Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP), Cambridge, 2018, pp. 617-621, doi: 10.1109/PDP2018.2018.00103

RVNoC : a framework for generating RISC-V NoC-based MPSoC

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Author: Elmohr, Mahmoud A.1; Eissa, Ahmed S.1; Ibrahim, Moamen2;
Organizations: 1Department of Communications and Electronics, Faculty of Engineering, Alexandria University, Alexandria, Egypt
2Center for Ubiquitous Computing, University of Oulu, Oulu, Finland
3Mentor Graphics, Cairo, Egypt
4Department of Computer and Systems Engineering, Ain Shams University, Cairo, Egypt
5Department of Computer Science, Faculty of Computers and Informatics, Benha University, Egypt
Format: article
Version: accepted version
Access: open
Online Access: PDF Full Text (PDF, 0.2 MB)
Persistent link: http://urn.fi/urn:nbn:fi-fe2020052739317
Language: English
Published: Institute of Electrical and Electronics Engineers, 2018
Publish Date: 2020-05-27
Description:

Abstract

With the increase in the number of cores embedded on a chip; The main challenge for Multiprocessor System-on-Chip (MPSoC) platforms is the interconnection between that massive number of cores. Networks-on-Chip (NoC) was introduced to solve that challenge, by providing a scalable and modular solution for communication between the cores. In this paper, we introduce a configurable MPSoC framework called RVNoC that generates synthesizable RTL that can be used in both ASIC and FPGA implementations. The proposed framework is based on the open source RISC-V Instruction Set Architecture (ISA) and an open source configurable flit-based router for interconnection between cores, with a core network interface of our design to connect each core with its designated router. A benchmarking environment is developed to evaluate variant parameters of the generated MPSoC. Synthesis of a single building block containing a single core without any peripherals, a router, and a core network interface, using 45nm technology, shows an area of 102.34 kilo Gate Equivalents (kGE), a maximum frequency of 250 MHz, and a 9.9 μW/MHz power consumption.

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Series: Proceedings Euromicro Workshop on Parallel and Distributed Processing
ISSN: 1066-6192
ISSN-E: 2377-5750
ISSN-L: 1066-6192
ISBN: 978-1-5386-4975-6
ISBN Print: 978-1-5386-4976-3
Pages: 617 - 621
DOI: 10.1109/PDP2018.2018.00103
OADOI: https://oadoi.org/10.1109/PDP2018.2018.00103
Host publication: 26th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2018
Host publication editor: Kotenko, I.
Merelli, I.
Lio, P.
Conference: Euromicro International Conference on Parallel, Distributed, and Network-Based Processing
Type of Publication: A4 Article in conference proceedings
Field of Science: 213 Electronic, automation and communications engineering, electronics
Subjects:
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