University of Oulu

Shaheen, R.A., Rahkonen, T. & Pärssinen, A. Design of a 40 GHz low noise amplifier using multigate technique for cascode devices. Analog Integr Circ Sig Process (2020). https://doi.org/10.1007/s10470-020-01722-w

Design of a 40 GHz low noise amplifier using multigate technique for cascode devices

Saved in:
Author: Shaheen, Rana Azhar1; Rahkonen, Timo1; Pärssinen, Aarno1
Organizations: 1University of Oulu, Oulu, Finland
Format: article
Version: published version
Access: open
Online Access: PDF Full Text (PDF, 2 MB)
Persistent link: http://urn.fi/urn:nbn:fi-fe2020102287339
Language: English
Published: Springer Nature, 2020
Publish Date: 2020-10-22
Description:

Abstract

Increased parasitic components in silicon-based nanometer (nm) scale active devices have various performance trade-offs between optimizing the key parameters, for example, maximum frequency of oscillation (𝑓𝑚𝑎𝑥, gate resistance and capacitance, etc. A common-source cascode device is commonly used in amplifier designs at RF/millimeter-wave (mmWave) frequencies. In addition to intrinsic parasitic components, extrinsic components due to wiring and layout effects, are also critical for performance and accurate modelling of the devices. In this work, a comparison of two different layout techniques for cascode devices is presented to optimize the extrinsic parasitic elements, such as gate resistance. A multi-gate or multi-port layout technique is proposed for optimizing the gate resistance (𝑟𝑔). Extracted values from measurement results show reduction of 10% in 𝑟𝑔 of multi-gate layout technique compared to a conventional gate-above-device layout for cascode devices. However, conventional layout exhibits smaller gate-to-source and gate-to-drain capacitances which leads to better performance in terms of speed, i.e. 𝑓𝑚𝑎𝑥. An LNA is designed at 40 GHz frequency using proposed multi-gate cascode device. LNA achieves a measured peak gain of 10.2 dB and noise figure of 4.2 dB at 40 GHz. All the structures are designed and fabricated using 45 nm CMOS silicon on insulator (SOI) technology.

see all

Series: Analog integrated circuits and signal processing
ISSN: 0925-1030
ISSN-E: 1573-1979
ISSN-L: 0925-1030
Volume: Online First
Issue: Online First
Pages: 1 - 11
DOI: 10.1007/s10470-020-01722-w
OADOI: https://oadoi.org/10.1007/s10470-020-01722-w
Type of Publication: A1 Journal article – refereed
Field of Science: 213 Electronic, automation and communications engineering, electronics
Subjects:
5G
LNA
RF
SOI
Funding: The authors would like to thank Nokia Corporation for financial support and Global Foundries for support in process technology. Lab assistance from Matti Polojarvi is highly acknowledged. This research has been also in part financially supported by Academy of Finland 6Genesis Flagship (Grant 318927).
Academy of Finland Grant Number: 318927
Detailed Information: 318927 (Academy of Finland Funding decision)
Copyright information: © The Authors 2020. This article is licensed under a Creative Commons Attribution 4.0 International License, which permits use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons licence, and indicate if changes were made. The images or other third party material in this article are included in the article's Creative Commons licence, unless indicated otherwise in a credit line to the material. If material is not included in the article's Creative Commons licence and your intended use is not permitted by statutory regulation or exceeds the permitted use, you will need to obtain permission directly from the copyright holder. To view a copy of this licence, visit http://creativecommons.org/licenses/by/4.0/.
  https://creativecommons.org/licenses/by/4.0/