H. Lai, P. (2020). Analysis and implementation of SDF Radix-2 FFT processor using VERILOG Hardware Description Language. International Journal of Advanced Trends in Computer Science and Engineering, 9(4), 5185–5189. https://doi.org/10.30534/ijatcse/2020/144942020
Analysis and implementation of sdf radix-2 fft processor using verilog hardware description language
|Author:||Lai, Phuong H.1; Hoang, Manh2; Tran, Viet Q.2;|
1Dept. of Computing Fundamentals, FPT University, Hanoi, Vietnam
2ICT Department, FPT University, Hanoi, Vietnam
3Center of Machine Vision & Signal Analysis, University of Oulu, Finland
|Online Access:||PDF Full Text (PDF, 0.6 MB)|
|Persistent link:|| http://urn.fi/urn:nbn:fi-fe2020112092225
The World Academy of Research in Science and Engineering,
|Publish Date:|| 2020-11-20
This paper will study a novel system on chip (SoC) design for fast Fourier transform (FFT) module. We first explain the role and position of FFT module in a digital intelligent system. Then, the discrete Fourier transform (DFT) and decimation in frequency (DIF) Radix-2 butterfly FFT algorithm is explained in detail, mathematically. In addition, the analysis of a simple pipeline FFT processor and a single-path delay feedback pipeline FFT processor based on SDF Radix-2 algorithm are discussed. Finally, the implementation and verification of proposed FFT processor are performed VERILOG hardware description language (HDL).
International journal of advanced trends in computer science and engineering
|Pages:||5185 - 5189|
|Type of Publication:||
A1 Journal article – refereed
|Field of Science:||
213 Electronic, automation and communications engineering, electronics
This work is supported by FPT University, Hanoi, Vietnam. We would like to thank Dr. Nguyen Manh Duc (G2Touch Company, Republic of Korea) for his useful suggestions, and Dr. Nguyen Ha Phong for his advices.
© The Authors 2020.