Arithmetic tracking adaptive SAR ADC for signals with low-activity periods
|Author:||Inanlou, Reza1; Safarpour, Mehdi2; Silvén, Olli2|
1School of Electrical and Computer Engineering, University of Tehran, Iran
2Center for Machine Vision and Signal Analysis (CMVS), University of Oulu, Finland
|Online Access:||PDF Full Text (PDF, 1.6 MB)|
|Persistent link:|| http://urn.fi/urn:nbn:fi-fe2020120198833
Institute of Electrical and Electronics Engineers,
|Publish Date:|| 2020-12-01
This paper introduces a novel arithmetic tracking algorithm for successive approximation ADCs, and presents its analysis. The algorithm utilizes low activity signal periods to cut the ADC energy dissipation by reducing the number of required bit-cycles. The approach determines the required step size, and bypasses conversion cycles when signal activity is low, without compromising the precision or sampling rate. The required first-order predictions and boundary checkings are performed with simple digital circuits. A lowered number of cycles paired with reduced voltage variations across DAC capacitors yields power savings. The solution has been simulated in a 90 nm CMOS process using HSPICE, demonstrating a 10-bit tracking SAR ADC. The proposed ADC was examined with low activity signals such as EEG, ECG, etc. The results predict from 5.8 μW to 27.6 μW dissipation when the sampling rates range from 32 kHz to 800 kHz, respectively.
|Pages:||211621 - 211629|
|Type of Publication:||
A1 Journal article – refereed
|Field of Science:||
213 Electronic, automation and communications engineering, electronics
This work was supported by the 6G Flagship research programme under Academy of Finland Grant 318927.
|Academy of Finland Grant Number:||
318927 (Academy of Finland Funding decision)
© The Authors 2020. This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/.