University of Oulu

H. Gamage, V. Ranasinghe, N. Rajatheva and M. Latva-aho, "Low Latency Decoder for Short Blocklength Polar Codes," 2020 European Conference on Networks and Communications (EuCNC), Dubrovnik, Croatia, 2020, pp. 305-310, doi: 10.1109/EuCNC48522.2020.9200964

Low latency decoder for short blocklength polar codes

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Author: Gamage, Heshani1; Ranasinghe, Vismika1; Rajatheva, Nandana1;
Organizations: 1Centre for Wireless Communications, University of Oulu, Finland
Format: article
Version: accepted version
Access: open
Online Access: PDF Full Text (PDF, 0.6 MB)
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Language: English
Published: Institute of Electrical and Electronics Engineers, 2020
Publish Date: 2021-02-19


Polar codes have been gaining a lot of interest due to it being the first coding scheme to provably achieve the symmetric capacity of a binary memoryless channel with an explicit construction. However, the main drawback of polar codes is the low throughput of its successive cancellation (SC) decoding. Simplified SC decoding algorithms of polar codes can be used to reduce the latency of the polar decoder by faster processing of specific sub-codes in the polar code. By combining simplified SC with a list decoding technique, such as SC list (SCL) decoding, polar codes can cater to the two conflicting requirements of high reliability and low latency in ultra-reliable low-latency (URLLC) communication systems. Simplified SC algorithm recognises some special nodes in the SC decoding tree, corresponding to the specific subcodes in the polar code construction, and efficiently prunes the SC decoding tree, without traversing the sub-trees and computing log-likelihood ratios (LLRs) for each child node. However, this decoding process still suffers from the latency associated with the serial nature of SC decoding. We propose some new algorithms to process new types of node patterns that appear within multiple levels of pruned sub-trees and it enables to process certain nodes in parallel. In short blocklength polar codes, our proposed algorithms can achieve up to 13% latency reduction from fast-simplified SC [1] without any performance degradation. Furthermore, it can achieve up to 27% latency reduction if small error-correcting performance degradation is allowed.

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Series: European Conference on Networks and Communications
ISSN: 2475-6490
ISSN-E: 2575-4912
ISSN-L: 2475-6490
ISBN: 978-1-7281-4355-2
ISBN Print: 978-1-7281-4356-9
Article number: 9200964
DOI: 10.1109/EuCNC48522.2020.9200964
Host publication: 2020 European Conference on Networks and Communications (EuCNC)
Conference: European Conference on Networks and Communications
Type of Publication: A4 Article in conference proceedings
Field of Science: 213 Electronic, automation and communications engineering, electronics
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