S. Shahabuddin, I. Hautala, M. Juntti and C. Studer, "ADMM-Based Infinity-Norm Detection for Massive MIMO: Algorithm and VLSI Architecture," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 4, pp. 747-759, April 2021, doi: 10.1109/TVLSI.2021.3056946
ADMM-based infinity-norm detection for massive MIMO : algorithm and VLSI architecture
|Author:||Shahabuddin, Shahriar1; Hautala, Ilkka1; Juntti, Markku2;|
1Mobile Networks, Nokia, Oulu, Finland
2Centre for Wireless Communications, University of Oulu, Finland
3Department of Information Technology and Electrical Engineering at ETH Zurich, Zurich, Switzerland
|Online Access:||PDF Full Text (PDF, 0.7 MB)|
|Persistent link:|| http://urn.fi/urn:nbn:fi-fe2021062239365
Institute of Electrical and Electronics Engineers,
|Publish Date:|| 2021-06-22
In this article, we propose a novel data detection algorithm and a corresponding VLSI design for massive multiuser (MU) multiple-input–multiple-output (MIMO) wireless systems. Our algorithm uses alternating direction method of multipliers (ADMM)-based infinity-norm-constrained equalization and is called ADMIN. ADMIN is an iterative algorithm that outperforms linear detectors by a large margin when the ratio between the numbers of base-station (BS) and user antennas is small. In the first iteration, ADMIN computes the linear minimum mean-square error (MMSE) solution, which is sufficient when the ratio between the numbers of BS and user antennas is large. We develop time-shared and iterative VLSI architectures for LDL-decomposition-based soft-output ADMIN supporting 16- and 32-user systems. We present application-specific integrated circuit (ASIC) designs for 16–64 antenna base stations in 28-nm CMOS that supports up to 64 quadrature amplitude modulation (QAM). The 16-user ADMIN ASIC achieves 303 Mb/s while dissipating 85 mW. The 32-user ADMIN ASIC achieves 287 and 241 Mb/s while dissipating 121 and 135 mW for 32 and 64 BS antennas, respectively. ADMIN has also been implemented on a Xilinx Virtex-7 field-programmable gate array (FPGA) and is compared with state-of-the-art massive MIMO data detectors.
IEEE transactions on very large scale integration (VLSI) systems
|Pages:||747 - 759|
|Type of Publication:||
A1 Journal article – refereed
|Field of Science:||
213 Electronic, automation and communications engineering, electronics
The research was supported financially by Academy of Finland 6Genesis Flagship (grant 318927). The work of C. Studer was supported in part by ComSenTer, one of six centers in JUMP, an SRC program sponsored by DARPA, by an ETH Research Grant, and by the US National Science Foundation (NSF) under grants CNS-1717559 and ECCS-1824379.
|Academy of Finland Grant Number:||
318927 (Academy of Finland Funding decision)
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