M. Safarpour, R. Inanlou and O. Silvén, "Algorithm Level Error Detection in Low Voltage Systolic Array," in IEEE Transactions on Circuits and Systems II: Express Briefs, doi: 10.1109/TCSII.2021.3094923
Algorithm level error detection in low voltage systolic array
|Author:||Safarpour, Mehdi1; Inanlou, Reza2; Silvén, Olli1|
1Center for Machine Vision and Signal Analysis, University of Oulu, Oulu, Finland
2School of Electrical and Computer Engineering, University of Tehran, Tehran, Iran
|Online Access:||PDF Full Text (PDF, 2.8 MB)|
|Persistent link:|| http://urn.fi/urn:nbn:fi-fe2021080341988
Institute of Electrical and Electronics Engineers,
|Publish Date:|| 2021-08-03
In this brief an approach is proposed to achieve energy savings from reduced voltage operation. The solution detects timing-errors by integrating Algorithm Based Fault Tolerance (ABFT) into a digital architecture. The approach has been studied with a systolic array matrix multiplier operating at reduced voltages, detecting errors on-the-fly to avoid energy demanding memory round-trips. The analysis of the solution has been done using analog-digital co-simulation to extract the transient behavior under different voltages and clock frequencies. HSPICE simulations using 90nm CMOS transistor models, and experiments by reducing operation voltage of an FPGA device were carried out. HSPICE simulations, showed possibility of 10x increase in energy-efficiency by approaching near-threshold region.
IEEE transactions on circuits and systems. II, Express briefs
|Pages:||1 - 5|
|Type of Publication:||
A1 Journal article – refereed
|Field of Science:||
113 Computer and information sciences
213 Electronic, automation and communications engineering, electronics
This work was supported by 6G Flagship research programme under Academy of Finland Grant 318927.
|Academy of Finland Grant Number:||
318927 (Academy of Finland Funding decision)
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