University of Oulu

S. Shahabuddin, M. A. Albreem, M. S. Shahabuddin, Z. Khan and M. Juntti, "FPGA Implementation of Stair Matrix based Massive MIMO Detection," 2021 IEEE 12th Latin America Symposium on Circuits and System (LASCAS), 2021, pp. 1-4, doi: 10.1109/LASCAS51355.2021.9459171

FPGA implementation of stair matrix based massive MIMO detection

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Author: Shahabuddin, Shahriar1; Albreem, Mahmoud A.1,2; Shahabuddin, Mohammad Shahanewaz3;
Organizations: 1Centre for Wireless Communications, University of Oulu, Finland
2A’Sharqiyah University, Oman
3Vaasa University of Applied Science, Finland
Format: article
Version: accepted version
Access: open
Online Access: PDF Full Text (PDF, 0.3 MB)
Persistent link: http://urn.fi/urn:nbn:fi-fe2021102151919
Language: English
Published: Institute of Electrical and Electronics Engineers, 2021
Publish Date: 2021-10-21
Description:

Abstract

Approximate matrix inversion based methods is widely used for linear massive multiple-input multiple-output (MIMO) received symbol vector detection. Such detectors typically utilize the diagonally dominant channel matrix of a massive MIMO system. Instead of diagonal matrix, a stair matrix can be utilized to improve the error-rate performance of a massive MIMO detector. In this paper, we present very large-scale integration (VLSI) architecture and field programmable gate array (FPGA) implementation of a stair matrix based iterative detection algorithm. The architecture supports a base station with 128 antennas, 8 users with single antenna, and 256 quadrature amplitude modulation (QAM). The stair matrix based detector can deliver a 142.34 Mbps data rate and reach a clock frequency of 258 MHz in a Xilinx Virtex -7FPGA. The detector provides superior error-rate performance and higher scaled throughput than most contemporary massive MIMO detectors.

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Series: IEEE Latin American Symposium on Circuits and Systems
ISSN: 2330-9954
ISSN-E: 2473-4667
ISSN-L: 2330-9954
ISBN: 978-1-7281-7670-3
ISBN Print: 978-1-7281-7671-0
Article number: 9459171
DOI: 10.1109/LASCAS51355.2021.9459171
OADOI: https://oadoi.org/10.1109/LASCAS51355.2021.9459171
Host publication: 12th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2021
Conference: IEEE Latin American Symposium on Circuits and Systems
Type of Publication: A4 Article in conference proceedings
Field of Science: 213 Electronic, automation and communications engineering, electronics
Subjects:
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