M. Safarpour, L. Xun, G. V. Merrett and O. Silvén, "A High-Level Approach for Energy Efficiency Improvement of FPGAs by Voltage Trimming," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, doi: 10.1109/TCAD.2021.3127153
A high-level approach for energy efficiency improvement of FPGAs by voltage trimming
|Author:||Safarpour, Mehdi1; Xun, Lei2; Merrett, Geoff V.2;|
1Center for Machine Vision and Signal Analysis, University of Oulu, Oulu, Finland
2School of Electronics and Computer Science, University of Southampton, UK
|Online Access:||PDF Full Text (PDF, 4.1 MB)|
|Persistent link:|| http://urn.fi/urn:nbn:fi-fe2021120959940
Institute of Electrical and Electronics Engineers,
|Publish Date:|| 2021-12-09
Chip manufacturers define voltage margins on top of the “best-case” operational voltage of their chips to ensure reliable functioning in the worst case settings. The margins guarantee correctness of operation, but at the cost of performance and power efficiency. Violating the margins is tempting to save energy, but might lead to timing errors. This paper proposes an algorithmic solution that enables reliable removal of the margins by detecting errors on the fly. In contrast to previous approaches that require special hardware to detect timing errors, the proposed method is fully implementable using high-level synthesis tools without reliance on additional hardware. The approach is demonstrated using a 32×32 matrix-matrix multiplication and a simple multi-layer neural network implemented on two Xilinx ZC702 Field-Programmable Gate Array (FPGA) System-on-Chip (SoC) platforms, showcasing its utility in detecting errors that may originate from different sources of logic circuits, clock tree or memory. Results show that the energy dissipation is halved, while the implementation is clocked at 2.5x faster than specified by the design tool of the vendor.
IEEE transactions on computer-aided design of integrated circuits and systems
|Type of Publication:||
A1 Journal article – refereed
|Field of Science:||
213 Electronic, automation and communications engineering, electronics
This work was supported by 6G Flagship research programme under Academy of Finland Grant 318927.
|Academy of Finland Grant Number:||
318927 (Academy of Finland Funding decision)
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