Abstract

Operating at reduced voltage is an effective technique for improving the energy efficiency of computing. However, the approach is constrained by its exacerbated sensitivity to Process, Voltage, and Temperature (PVT) variations, which under throughput constraints challenges finding the energy minimizing voltage-frequency operating point. Commonly utilized design approaches for adaptive voltage scaling are based on timing slack measurement or speculation techniques that require adding extra hardware, e.g., Error Detection Sequence (EDS) circuits, that substantially increase the design complexity, and are not applicable for already fabricated designs. In this paper, instead of circuit-level techniques, a low-cost algorithmic error detection method is proposed as the enabler for reduced voltage operation of Fast Fourier Transform (FFT) accelerators. Without requiring neither gate-level nor circuit-level modifications, the method works based on an intrinsic property of the Fourier transform, i.e., Parsevalfs identity. The method is demonstrated on a System-on-Chip (SoC) that integrates a Field-Programmable Gate Array (FPGA) made to operate at reduced voltages. The fault detection capability is profiled using the demonstration test bench, implemented both as software and as hardware. In the experiments, a.43% reduction in power consumption was achieved without sacrificing the throughput and reliability. The overheads of the proposed fault detection approach scale sub-linearly with respect to FFT size and are ≤10% for 1024-point FFT.