University of Oulu

SystemVerilog-kieleen ja UVM-verifiointimenetelmään perustuva parametrisoitava testipenkki

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Author: Tikka, Seppo
Organizations: 1University of Oulu, Faculty of Technology, Department of Electrical Engineering, Electrical Engineering
Format: ebook
Version: published version
Access: restricted
Persistent link:
Language: Finnish
Published: Oulu : S. Tikka, 2013
Publish Date: 2013-06-03
Physical Description: 51 p.
Thesis type: Master's thesis (tech)
Tutor: Lahti, Jukka
Reviewer: Rahkonen, Timo
Lahti, Jukka
Copyright information: This thesis' fulltext and abstract availability is restricted and they are only accessible from certain Jultika-workstations on the library premises.