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SystemVerilog-kieleen ja UVM-verifiointimenetelmään perustuva parametrisoitava testipenkki |
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| Author: | Tikka, Seppo1 |
| Organizations: |
1University of Oulu, Faculty of Technology, Department of Electrical Engineering, Electrical Engineering |
| Format: | ebook |
| Version: | published version |
| Access: | restricted |
| Theses with restricted access are only available for reading on the e-thesis workstations. | |
| Pages: | 51 |
| Persistent link: | http://urn.fi/URN:NBN:fi:oulu-201306021441 |
| Language: | Finnish |
| Published: |
Oulu :
S. Tikka,
2013
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| Publish Date: | 2013-06-03 |
| Thesis type: | Master's thesis (tech) |
| Tutor: |
Lahti, Jukka |
| Reviewer: |
Rahkonen, Timo Lahti, Jukka |
| Subjects: | |
| Copyright information: |
© Seppo Tikka, 2013. This publication is copyrighted. You may download, display and print it for your own personal use. Commercial use is prohibited. |