|
|
High-level synthesis design flow in FPGA design |
|---|---|
| Author: | Kivimäki, Iiro1 |
| Organizations: |
1University of Oulu, Faculty of Information Technology and Electrical Engineering, Department of Electrical Engineering, Electrical Engineering |
| Format: | ebook |
| Version: | published version |
| Access: | restricted |
| Theses with restricted access are only available for reading on the e-thesis workstations. | |
| Pages: | 60 |
| Persistent link: | http://urn.fi/URN:NBN:fi:oulu-201605051650 |
| Language: | English |
| Published: |
Oulu :
I. Kivimäki,
2016
|
| Publish Date: | 2016-05-09 |
| Thesis type: | Master's thesis (tech) |
| Tutor: |
Lahti, Jukka |
| Reviewer: |
Häkkinen, Juha Lahti, Jukka |
| Subjects: | |
| Copyright information: |
© Iiro Kivimäki, 2016. This publication is copyrighted. You may download, display and print it for your own personal use. Commercial use is prohibited. |