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I2S-väyläliitynnän toteutus FPGA-piirille |
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| Author: | Junttila, Joel1 |
| Organizations: |
1University of Oulu, Faculty of Information Technology and Electrical Engineering, Electrical Engineering |
| Format: | ebook |
| Version: | published version |
| Access: | open |
| Online Access: | PDF Full Text (PDF, 1 MB) |
| Pages: | 17 |
| Persistent link: | http://urn.fi/URN:NBN:fi:oulu-201612303346 |
| Language: | Finnish |
| Published: |
Oulu :
J. Junttila,
2016
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| Publish Date: | 2017-01-02 |
| Thesis type: | Bachelor's thesis |
| Description: |
Tutkimuksen aiheena oli tehdä toimiva I2S-väylä protokolla ja tutkia voiko piiriä luoda FPGA-piirille. Piirille tehtiin RTL-toteutus SystemVerilog kovonkuvauskielellä. Sen jälkeen piirille ajettiin FPGA-synteesi Alteran Cyclone 5 GX FPGA-piirille. Suurin kellotaajuus oli 263,5 MHz ja logiikkalohkoja käytettiin 18 kappaletta. Lopuksi tutkittiin päästiinkö tavotteisiin.
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The subject of the Bachelor’s Thesis was to create a workable I2S bus protocol and to examine if it is possible to create the I2S circuit to FPGA. RTL-model was made to the circuit with a hardware description language SystemVerilog. After that FPGA synthesis was execute to the Altera’s Cyclone 5 GX. The maximum clock frequency was 263,5 MHz and 18 logic blocks were used. Finally, the end results were examined to see if they met the objectives of this study.
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| Copyright information: |
© Joel Junttila, 2016. This publication is copyrighted. You may download, display and print it for your own personal use. Commercial use is prohibited. |