University of Oulu

Digitaalipiirien alustustavat ja niiden kuvaaminen SystemVerilog- ja VHDL-kielillä

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Author: Kaijansaari, Matti1
Organizations: 1University of Oulu, Faculty of Information Technology and Electrical Engineering, Electrical Engineering
Format: ebook
Version: published version
Access: restricted
  Theses with restricted access are only available for reading on the e-thesis workstations.
Pages: 19
Persistent link: http://urn.fi/URN:NBN:fi:oulu-201905141764
Language: Finnish
Published: Oulu : M. Kaijansaari, 2019
Publish Date: 2019-05-20
Thesis type: Bachelor's thesis
Subjects:
Copyright information: © Matti Kaijansaari, 2019. This publication is copyrighted. You may download, display and print it for your own personal use. Commercial use is prohibited.