FPGA implementation of stair matrix based massive MIMO detection
Shahabuddin, Shahriar; Albreem, Mahmoud A.; Shahabuddin, Mohammad Shahanewaz; Khan, Zaheer; Juntti, Markku (2021-06-28)
S. Shahabuddin, M. A. Albreem, M. S. Shahabuddin, Z. Khan and M. Juntti, "FPGA Implementation of Stair Matrix based Massive MIMO Detection," 2021 IEEE 12th Latin America Symposium on Circuits and System (LASCAS), 2021, pp. 1-4, doi: 10.1109/LASCAS51355.2021.9459171
© 2021 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
https://rightsstatements.org/vocab/InC/1.0/
https://urn.fi/URN:NBN:fi-fe2021102151919
Tiivistelmä
Abstract
Approximate matrix inversion based methods is widely used for linear massive multiple-input multiple-output (MIMO) received symbol vector detection. Such detectors typically utilize the diagonally dominant channel matrix of a massive MIMO system. Instead of diagonal matrix, a stair matrix can be utilized to improve the error-rate performance of a massive MIMO detector. In this paper, we present very large-scale integration (VLSI) architecture and field programmable gate array (FPGA) implementation of a stair matrix based iterative detection algorithm. The architecture supports a base station with 128 antennas, 8 users with single antenna, and 256 quadrature amplitude modulation (QAM). The stair matrix based detector can deliver a 142.34 Mbps data rate and reach a clock frequency of 258 MHz in a Xilinx Virtex -7FPGA. The detector provides superior error-rate performance and higher scaled throughput than most contemporary massive MIMO detectors.
Kokoelmat
- Avoin saatavuus [31657]